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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information Low Voltage PLL Clock Driver
The MPC932 is a 3.3V compatible PLL based clock driver device targetted for zero delay applications. The device provides 6 outputs for driving clock loads plus a single dedicated PLL feedback clock output. The dedicated feedback output gives the user six choices of input multiplcation factors: x1, x1.25, x1.5, x2, x2.5 and x3.
MPC932
* * * * * * * *
6 Low Skew Clock Outputs 1 Dedicated PLL Feedback Output Individual Output Enable Control Fully Integrated PLL Output Frequency Up TO 120MHz 32-lead TQFP Packaging 3.3V VCC 100ps Cycle-Cycle Jitter
LOW VOLTAGE PLL CLOCK DRIVER
The MPC932 provides individual output enable control. The enables are synchronized to the internal clock such that upon assertion the shut down signals will hold the clocks LOW without generating a runt pulse on the outputs. The shut down pins provide a means of powering down certain portions of a system or a means of disabling outputs when the full compliment are not required for a specific design. The shut down pins will disable the outputs when driven LOW. A common shut down pin is provided to disable all of the outputs (except the feedback output) with a single control signal.
FA SUFFIX TQFP PACKAGE CASE 873A-02
Two feedback select pins are provided to select the multiplication factor of the PLL. The MPC932 provides six multiplication factors: x1, x1.25, x1.5, x2, x2.5 and x3. In the x1.25 and x2.5 modes, the QFB output will not provide a 50% duty cycle. The phase detector of the MPC932 only monitors rising edges of its feedback signals, thus for this function a 50% duty cycle is not required. As the QFB signal can also be used to drive other clocks in a system it is important the user understand that the duty cycle will not be 50%. In the x1 and x1.5 modes the QFB output will produce 50% duty cycle signals. The MPC932 provides two pins for use in system test and debug operations. The MR/OE input will force all of the outputs into a high impedance state to allow for back driving the outputs during system test. In addition the PLL_EN pin allows the user to bypass the PLL and drive the outputs directly through the Ref_CLK input. Note the Ref_CLK signal will be routed through the dividers so that it will take several transitions on the Ref_CLK input to create a transition on the outputs. The MPC932 is fully 3.3V compatible and requires no external loop filter components. All of the inputs are LVCMOS/LVTTL compatible and the outputs produce rail-to-rail 3.3V swings. For series terminated applications each output can drive two series terminated 50 transmission lines. For parallel terminated lines the device can drive terminations of 50 into VCC/2. The device is packaged in a 32-lead TQFP package to provide the optimum combination of performance, board density and cost.
This document contains information on a new product. Specifications and information herein are subject to change without notice. 11/96
(c) Motorola, Inc. 1996
1
REV 0
MPC932
Pinout: 32-Lead TQFP Package (Top View)
GNDO GNDO
FUNCTION TABLES
VCCO Q4 Q5 SDn, COM_SD 0 1 Qn Held LOW Enabled PLL Status Test Mode PLL Enabled PLL Status Disabled Enabled
VCCO 22
Q2
24 Q1 VCCO Q0 GNDO SD2 SD0:1 MODE VCCA 25 26 27 28 29 30 31 32 1
23
Q3 21
20
19
18
17 16 15 14 GND_QFB QFB VCCO_QFB FB_In SD3 SD4 SD5 GNDA MODE 0 0 0 0 1 1 1 1 FBSEL1 0 0 1 1 0 0 1 1 FBSEL0 0 1 0 1 0 1 0 1 Qn VCO/4 VCO/4 VCO/4 NA VCO/4 VCO/4 VCO/4 NA QFB VCO/8 VCO/10 VCO/12 NA VCO/4 VCO/5 VCO/6 NA PLL_En 0 1 MR/OE 0 1
MPC932
13 12 11 10 9
2
3
4
5
6
7
8
REF_CLK
COM_SD
PLL_EN
VCCI
MR/OE
FBSEL0
FBSEL1
GNDI
LOGIC DIAGRAM
SD0:1 PLL_EN /4 /4 /2 /5 /6 SD2 STOP STOP SD3 SD4 STOP STOP SD5 QFB FBSEL0 FBSEL1 Q4 Q5 Q2 Q3 STOP STOP Q0 Q1
REF_CLK FB_In MODE MR/OE COM_SD
PLL 200-480MHz
MOTOROLA
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TIMING SOLUTIONS BR1333 -- REV 5
MPC932
Qn
SDn
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
Symbol VCC VI IIN TStor Supply Voltage Input Voltage Input Current Storage Temperature Range -40 Parameter Min -0.3 -0.3 Max 4.6 VDD + 0.3 20 125 Unit V V mA C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied.
PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70C)
Symbol tr, tf fref Characteristic TCLK Input Rise/Falls Reference Input Frequency Note 1. Min Max 3.0 Note 1. Unit ns MHz Condition
frefDC Reference Input Duty Cycle 25 75 % 1. Maximum and Maximum input reference frequency is limited by the VCO lock range and the feedback divider.
DC CHARACTERISTICS (TA = 0 to 70C, VCC = 3.3V 5%)
Symbol VIH VIL VOH VOL IIN ICC ICCPLL CIN Characteristic Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Input Current Maximum Core Supply Current Maximum PLL Supply Current 15 2.4 0.5 120 100 20 4 Min 2.0 Typ Max 3.6 0.8 Unit V V V V A mA mA pF IOH = -20mA (Note 2.) IOL = 20mA (Note 2.) Note 3. Condition
Cpd 25 pF Per Output 2. The MPC932 outputs can drive series or parallel terminated 50 (or 50 to VCC/2) transmission lines on the incident edge (see Applications Info section). 3. Inputs have pull-up/pull-down resistors which affect input current.
TIMING SOLUTIONS BR1333 -- REV 5
3
MOTOROLA
MPC932
MPC932 AC CHARACTERISTICS (TA = 0 to 70C, VCC = 3.3V 5%)
Symbol fref tos fVCO fmax Characteristic Input Reference Frequency Output-to-Output Skew VCO Lock Range Maximum Output Frequency (/4) (/5) (/6) X - 150 tCYCLE/2 -750 0.1 2.0 2.0 100 X tCYCLE/2 500 200 Min Note 6. 200 Typ Max Note 6. 300 480 120 96 80 X + 150 tCYCLE/2 +750 1.0 8.0 10 Unit MHz ps MHz MHz Note 4. Condition
tpd tpw tr, tf tPLZ, tPHZ tPZL tjitter
Reference to EXT_FB Average Delay TCLK PECL_CLK Output Duty Cycle (Note 4.) Output Rise/Fall Time (Note 4.) Output Disable Time Output Enable Time Cycle-to-Cycle Jitter (Peak-to-Peak)
ps ps ns ns ns ps ms
fref = 50MHz; Note 7.
0.8 to 2.0V 50 to VCC/2 50 to VCC/2 Note 5.
tlock Maximum PLL Lock Time 10 4. Measured with 50 to VCC/2 termination. 5. See Applications Info section for more jitter information. 6. Input reference frequency is bounded by VCO lock range and feedback divide selection. 7. tpd measurement uses the averaging feature of the oscilliscope to remove the jitter component.
APPLICATIONS INFORMATION
MPC932 `0' `0' FBSEL0 FBSEL1 Qn 6 66MHz `1' `0' FBSEL0 FBSEL1
MPC932 Qn 6 83MHz
QFB 66MHz Input Ref FB_In
1
66MHz 66MHz Input Ref FB_In
QFB
1
66MHz
MPC932 `1' `0' FBSEL0 FBSEL1 Qn 6 75MHz `0' `1' FBSEL0 FBSEL1
MPC932 Qn 6 100MHz
QFB 60MHz Input Ref FB_In
1
60MHz 66MHz Input Ref FB_In
QFB
1
66MHz
Figure 2. MPC932 Potential Configurations (Mode = 1)
MOTOROLA
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TIMING SOLUTIONS BR1333 -- REV 5
MPC932
Power Supply Filtering The MPC932 is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The MPC932 provides separate power supplies for the output buffers (VCCO) and the internal PLL (VCCA) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCCA pin for the MPC932. adequate to eliminate power supply noise related problems in most designs. Driving Transmission Lines The MPC932 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 10 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to application note AN1091 in the Timing Solutions brochure (BR1333/D). In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC932 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 4 illustrates an output driving a single series terminated line vs two series terminated lines in parallel. When taken to its extreme the fanout of the MPC932 clock driver is effectively doubled due to its capability to drive multiple lines.
MPC932 OUTPUT BUFFER IN 7 RS = 43 ZO = 50 OutA
3.3V
RS=10-15 VCCA 22F MPC932 VCC 0.01F 0.01F
Figure 3. Power Supply Filter Figure 3 illustrates a typical power supply filter scheme. The MPC932 is most susceptible to noise with spectral content in the 1KHz to 1MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the VCCA pin of the MPC932. From the data sheet the IVCCA current (the current sourced through the VCCA pin) is typically 15mA (20mA maximum), assuming that a minimum of 3.0V must be maintained on the VCCA pin very little DC voltage drop can be tolerated when a 3.3V VCC supply is used. The resistor shown in Figure 3 must have a resistance of 10-15 to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20KHz. As the noise frequency crosses the series resonant point of an individual capacitor it's overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC932 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be
MPC932 OUTPUT BUFFER IN 7
RS = 43
ZO = 50 OutB0
RS = 43
ZO = 50 OutB1
Figure 4. Single versus Dual Transmission Lines The waveform plots of Figure 5 show the simulation results of an output driving a single line vs two lines. In both cases the drive capability of the MPC932 output buffers is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC932. The output waveform in Figure 5 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 43 series resistor plus the output impedance does not match the parallel combination of the
TIMING SOLUTIONS BR1333 -- REV 5
5
MOTOROLA
MPC932
line impedances. The voltage wave launched down the two lines will equal: VL = VS ( Zo / (Rs + Ro +Zo)) Zo = 50 || 50 Rs = 43 || 43 Ro = 7 VL = 3.0 (25 / (21.5 + 7 + 25) = 3.0 (25 / 53.5) = 1.40V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.8V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns).
3.0 OutA tD = 3.8956 OutB tD = 3.9386
Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 6 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched.
MPC932 OUTPUT BUFFER 7 RS = 36 ZO = 50
RS = 36
ZO = 50
2.5
VOLTAGE (V)
2.0 In 1.5
7 + 36 k 36 = 50 k 50 25 = 25 Figure 6. Optimized Dual Line Termination SPICE level output buffer models are available for engineers who want to simulate their specific interconnect schemes. In addition IV characteristics are in the process of being generated to support the other board level simulators in general use.
1.0
0.5
0 2 4 6 8 TIME (nS) 10 12 14
Figure 5. Single versus Dual Waveforms
MOTOROLA
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TIMING SOLUTIONS BR1333 -- REV 5
MPC932
OUTLINE DIMENSIONS
FA SUFFIX TQFP PACKAGE CASE 873A-02 ISSUE A
-T-, -U-, -Z- AE P B1
8
A A1
32 25
4X
0.20 (0.008) AB T-U Z
1
-T- B DETAIL Y
17
-U- V V1 AE
9
DETAIL Y -Z-
4X
9
S1 S
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
-AC-
BASE METAL
N
F
8X
D
M_ R
0.20 (0.008)
M
AC T-U Z
0.10 (0.004) AC
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
CE
SECTION AE-AE
X DETAIL AD
TIMING SOLUTIONS BR1333 -- REV 5
GAUGE PLANE
0.250 (0.010)
H
W
K
Q_
7
EE EE EE
J
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
MOTOROLA
MPC932
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MPC932/D TIMING SOLUTIONS BR1333 -- REV 5

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